1) Field of the Invention
This invention relates generally to planarization of insulating layers over a semiconductor device and particularly to a method of etching and chemical-mechanical polishing to planarize an insulating layer over raised portions of a semiconductor device and more particularly to a planarization method using an etch and two chemical-mechanical polishing processing steps.
2) Description of the Prior Art
In the conventional construction of integrated circuit structures, shallow trenches are formed into a substrate and the surface of the substrate are covered and the trenches are filled with a deposited oxide layer. Next, a planarization process such as an etch back or chemical-mechanical polish process is used to planarize the oxide layer which leaves a planar level surface. However, current planarization processes must be improved to better planarize oxide layers so that devices can be further miniaturized. Isolation processes and planarization processes must be improved to provide more uniform planarization layers over shallow trench isolation areas. Current chemical-mechanical polish (CMP) processes still produce non-uniform insulating layers (e.g., oxide) over active areas of various dimensions between trenches.
A recent approach to planarization is the reverse tone mask as described in U.S. Pat. No. 4,954,459 (Avanzino et al.). The approach improves planarization but adds a costly masking step. Moreover, the removal of oxide over all active areas (raised portions) causes "dishing" of oxide in the trenches. Dishing is caused by the locally faster CMP polish rate in areas that have less oxide coverage.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat No. 4,962,064 (Haskell et al.) shows that a conformal oxide insulating layer 30 and chemical-mechanical polish (CMP) process that uses a Polysilicon layer 40B (FIG. 7) as etch mask. However, Haskell's process can be improved to produce better CMP planarization by improving on the positions and thickness of the oxide layer overlying the raised portions.
U.S. Pat. No. 4,954,459(Avanzino et al.) shows an etch planarization process that uses a photoresist mask in registry with high regions of the dielectric layer and an etch back process. U.S. Pat. No. 5,494,854(Jain) shows planarization process with CMP using a dielectric stack.
U.S. Pat. No. 5,612,242 (Hsu) shows a method of forming a trench isolation in a CMOS transistor. A silicon nitride layer is deposited and etched back to form spacers on the side walls of the electrodes whereby slits are left between the field oxide layer and the spacers and between adjacent spacers. Trenches are formed by etching the silicon substrate in the slits. An oxide layer is formed to refill the trenches and then etched back to remove the spacers.
However, an improved process is still needed that produces a more planar trench oxide without CMP "dishing" effects and stringent etch requirements.